Field of the Invention
The invention relates to a trench capacitor with a selection transistor and a corresponding fabrication method. The invention is explained with regard to a trench capacitor that is used in a DRAM memory cell. For discussion purposes, the invention is described in respect of the formation of an individual memory cell.
Integrated circuits (ICs) or chips contain capacitors for the purpose of storing charge, such as, for example, a dynamic random access memory (DRAM). In such a case, the charge state in the capacitor represents a data bit.
A DRAM chip contains a matrix of memory cells that are disposed in the form of rows and columns and are addressed by word lines and bit lines. The reading of data from the memory cells or the writing of data to the memory cells is realized by activating suitable word lines and bit lines.
A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor includes, inter alia, two diffusion regions isolated from one another by a channel that is controlled by a gate. Depending on the direction of current flow, one diffusion region is referred to as the drain and the other as the source. The source region is connected to a bit line, the drain region is connected to the trench capacitor and the gate is connected to a word line. By the application of suitable voltages to the gate, the transistor is controlled such that a current flow between the drain region and the source region through the channel is switched on and off.
The charge stored in the capacitor decreases over time on account of leakage currents. Before the charge has decreased to a level below a threshold value, the storage capacitor must be refreshed. For this reason, these memories are referred to as dynamic RAM (DRAM).
The central problem in prior art DRAM variants based on a trench capacitor is the production of a sufficiently large capacitance for the trench capacitor. The problem will be aggravated in future by the advancing miniaturization of semiconductor components. The increase in the integration density means that the area available per memory cell and, thus, the capacitance of the trench capacitor decrease ever further.
Sense amplifiers require a sufficient signal level for reliably reading out the information situated in the memory cell. The ratio of the storage capacitance to the bit line capacitance is crucial in determining the signal level. If the storage capacitance is too low, the ratio may be too small for generating an adequate signal.
A lower storage capacitance likewise requires a higher refresh frequency, because the quantity of charge stored in the trench capacitor is limited by its capacitance and additionally decreases due to leakage currents. If the quantity of charge falls below a minimum quantity of charge in the storage capacitor, then it is no longer possible for the information stored therein to be read out by the connected sense amplifiers, the information is lost, and read errors arise.
One way of avoiding read errors is to reduce the leakage currents. Leakage currents can be reduced on the one hand by transistors and on the other hand by dielectrics, such as the capacitor dielectric, for example. An undesirably reduced retention time can be lengthened by these measures.
Stacked capacitors or trench capacitors are usually used in DRAMs. Examples of DRAM memory cells having a trench capacitor are given in U.S. Pat. No. 4,649,625 to Lu, U.S. Pat. No. 5,065,273 to Rajeevakumar, U.S. Pat. No. 5,512,767 to Noble, Jr., U.S. Pat. No. 5,641,694 to Kenney, U.S. Pat. No. 5,658,816 to Rajeevakumar, U.S. Pat. No. 5,691,549 to Lam et al., U.S. Pat. No. 5,736,760 to Hieda et al., U.S. Pat. No. 5,744,386 to Kenney, and U.S. Pat. No. 5,869,868 to Rajeevakumar.
A trench capacitor has a three-dimensional structure that is formed in a silicon substrate, for example. An increase in the capacitor electrode area and, thus, in the capacitance of the trench capacitor can be achieved, for example, by etching more deeply into the substrate and, thus, by deeper trenches. In such a case, the increase in the capacitance of the trench capacitor does not cause the substrate surface occupied by the memory cell to be enlarged. However, this method is also limited because the attainable etching depth of the trench capacitor depends on the trench diameter, and, during fabrication, it is only possible to attain specific, finite aspect ratios between the trench depth and trench diameter.
As the increase in the integration density advances, the substrate surface available per memory cell decreases ever further. The associated reduction in the trench diameter leads to a reduction in the capacitance of the trench capacitor. If the capacitance of the trench capacitor is dimensioned to be so low that the charge that can be stored is insufficient for entirely satisfactory readout by the sense amplifiers connected downstream, then read errors result.
The problem is solved, for example, in the publication N.C.C. Lou, IEDM 1988, page 588 et seq., by moving the transistor, which is usually situated next to the trench capacitor, to a position situated above the trench capacitor. As a result, the trench can take up a part of the substrate surface that is conventionally reserved for the transistor. Through such a configuration, the trench capacitor and the transistor share part of the substrate surface. The configuration is made possible by growing an epitaxial layer above the trench capacitor.
What is problematic, however, is the electrical connection of the trench capacitor to the transistor. To that end, N.C.C. Lou, TEDM 1988, page 588 et seq., describes a method in which lithographic alignment of the individual lithographic planes with respect to one another requires a minimum distance between trench capacitor and transistor. As a result, the memory cells in a memory cell array require a relatively large area and are unsuitable for integration in a large-scale integrated cell array.
Furthermore, Japanese Patent Document 10-321813 A, corresponding to U.S. Pat. No. 5,998,821 to Hieda et al., discloses a DRAM memory cell in which the selection transistor is situated in a subsequently grown, epitaxial silicon layer directly above the trench capacitor. A so-called xe2x80x9csurface strapxe2x80x9d diffusion layer 35 is provided to electrically connect the inner capacitor electrode 25 to the source/drain regions 34.
Furthermore, U.S. Pat. No. 5,843,820 to Lu discloses a DRAM memory cell in which the selection transistor is situated in a subsequently grown, epitaxial silicon layer above a horizontal trench capacitor.
However, U.S. Pat. No. 5,410,503 to Anzai discloses a memory cell having a selection transistor and a trench capacitor. In such a case, the selection transistor is disposed in a subsequently grown, epitaxial silicon layer and horizontally adjoins the trench capacitor, so that the source electrode is electrically conductively connected to the outer capacitor electrode.
It is accordingly an object of the invention to provide a memory with trench capacitor and selection transistor and method for fabricating it that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that electrically connects the trench capacitor to the transistor in a way that is suitable for a large scale integrated cell array.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a semiconductor memory, including a substrate and at least two memory cells. Each of the memory cells is disposed at least partly in the substrate. Each of the memory cells has a transistor having a drain region, a source region, and a channel, a first word line disposed between the source region and the drain region, a trench capacitor having an inner electrode, an outer electrode, and a dielectric layer disposed between the inner electrode and the outer electrode, a trench disposed in the substrate and filled with a conductive trench filling forming the inner electrode of the trench capacitor, an insulating covering layer disposed on the conductive trench filling, an epitaxial layer disposed on the substrate and at least partly on the insulating covering layer, the source region, the drain region, and the channel of the transistor disposed in the epitaxial layer, a trench isolation disposed in the substrate and in the epitaxial layer, the trench isolation insulating adjacent ones of the memory cells from one another, the trench isolation respectively extending into the inner electrode of each of two adjacent ones of the memory cells, the first word line disposed on the epitaxial layer and partly covering the trench, a first insulation encapsulation surrounding the first word line, a second word line disposed on the trench isolation, second insulation encapsulation surrounding the second word line, a contact trench having a self-aligned connection electrically connecting the conductive trench filling to the drain region, the contact trench disposed between the first word line with the first insulation encapsulation and the second word line with the second insulation encapsulation, and the trench isolation bounding the contact trench.
The idea on which the invention is based lies in the use of a self-aligned connection that electrically connects the trench capacitor to the transistor. In such a case, structures that are already present on a substrate are used for forming the self-aligned connection.
In accordance with another feature of the invention, the contact trench has a lower region and an insulation collar is disposed in the lower region.
In accordance with a further feature of the invention, the word lines with their insulation encapsulations are used as an etching mask for the formation of a contact trench. The self-aligned connection can subsequently be formed in the contact trench.
In accordance with an added feature of the invention, the trench isolation (STI) is used as an etching mask for the formation of a contact trench, in which the self-aligned connection is subsequently formed.
In accordance with an additional feature of the invention, there is provided an insulation collar situated in the lower region of the contact trench.
In accordance with yet another feature of the invention, there is provided a conductive material disposed on the conductive trench filling.
In accordance with yet a further feature of the invention, there is provided a conductive material disposed in the insulation collar, in the contact trench, and on the conductive trench filling.
In accordance with yet an added feature of the invention, there is provided a conductive material that contributes to the electrical connection between trench capacitor and transistor situated in the contact trench.
In accordance with yet an additional feature of the invention, there is provided a conductive cap disposed on the conductive material in the contact trench.
In accordance with again another feature of the invention, there is provided a conductive cap that likewise contributes to the electrical connection between trench capacitor and transistor is situated on the conductive material in the contact trench.
In accordance with again a further feature of the invention, the insulation collar extends from the insulating covering layer at least as far as the drain region, and the conductive material and the conductive cap are not directly connected to the substrate or to the epitaxial layer. As a result, the conductive material and the conductive cap are insulated to reduce leakage currents that could discharge the trench capacitor.
In accordance with again an added feature of the invention, the trench isolation reaches at least down to the depth of the insulating covering layer.
In accordance with again an additional feature of the invention, the trench isolation extends deeper into the substrate than a depth of the insulating covering layer.
With the objects of the invention in view, there is also provided a method for forming a semiconductor memory having a trench, and memory cells each having a transistor with a drain region, a source region, and a channel, a first word line disposed between the source region and the drain region, and a trench capacitor having an inner electrode, an outer electrode, and a dielectric layer disposed between the inner electrode and the outer electrode, includes the steps of providing a substrate with a trench, filling the trench with a conductive trench filling to form the inner electrode of the trench capacitor, forming an insulating covering layer on the conductive trench filling, growing an epitaxial layer on the surface of the substrate and partly covering the insulating covering layer with the epitaxial layer, forming a trench isolation at least in the epitaxial layer to insulate adjacent memory cells from one another, forming the first word line above the epitaxial layer, forming a second word line above the trench isolation, surrounding the first word line a first insulation encapsulation, surrounding the second word line a second insulation encapsulation, defining the source region and the drain region of the transistor in the epitaxial layer, etching a contact trench through the epitaxial layer and the insulating covering layer as far as the conductive trench filling utilizing the first word line with the first insulation encapsulation and the second word line with the second insulation encapsulation as an etching mask for the etching of the contact trench, and forming a self-aligned connection in the contact trench to electrically connect the conductive trench filling to the drain region.
In accordance with still another mode of the invention, the contact trench is formed in a self-aligned manner between the first and second word lines. This means that the first and second word lines with their first and second insulation encapsulations, respectively, are used as an etching mask for the formation of the contact trench.
In accordance with still a further mode of the invention, the trench isolation is formed as an etching mask for the formation of the contact trench.
In accordance with still an added mode of the invention, an insulation collar is advantageously formed in the contact trench. Furthermore, at least one conductive material that contributes to the electrical connection between trench capacitor and transistor is introduced in the contact trench.
In accordance with still an additional mode of the invention, a conductive cap that likewise contributes to the electrical connection is formed above the conductive material and above the insulation collar.
In accordance with another mode of the invention, the insulation collar is advantageously formed such that the conductive material and the conductive cap are electrically connected to the epitaxial layer only through the drain region. The configuration reduces leakage currents that can discharge the trench capacitor.
In accordance with a further mode of the invention, the epitaxial layer is doped in situ. As a result, the channel doping of the transistor and the well doping can be set as early as during the growth of the epitaxial layer. Furthermore, the formation of doping profiles with very steep slopes is made possible, which lead to small leakage currents and make the components scaleable.
In accordance with an added mode of the invention, an epitaxial closing joint is formed in the epitaxial layer, which is at least partly removed through the trench isolation and/or through the contact trench. Moreover, it is advantageous to orient the layout of the trench to a crystal orientation of the substrate such that the epitaxial closing joint becomes as small as possible.
In accordance with an additional mode of the invention, the insulating covering layer is formed before the removal of a hard mask that has been used to pattern the trench. As a result, it is possible to form the insulating covering layer selectively in the trench on the conductive trench filling.
In accordance with yet another mode of the invention, a temperature step is carried out after growing the epitaxial layer.
In accordance with yet a further mode of the invention, the epitaxial layer is annealed after growing the epitaxial layer.
It is advantageous to treat the epitaxial layer with a thermal step that reduces the defects in the epitaxial layer and anneals the epitaxial closing joint. In such a case, the crystal structure of the epitaxial closing joint is as far as possible completely reconstructed.
In accordance with yet an added mode of the invention, the epitaxial layer is planarized after growing the epitaxial layer. It is advantageous to treat the epitaxial layer with a planarization step that smoothes and partly etches back the surface of the epitaxial layer.
In accordance with a concomitant feature of the invention, the word lines and their insulation encapsulations are formed as lateral edge webs (spacers) on the sidewalls of the trench isolation. The configuration has the advantage that the word lines can have a width that lies below the smallest lithography dimension F.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory with trench capacitor and selection transistor and method for fabricating it, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.